Much radio communication equipment, such as mobile phones, comprises a receiver (or a transceiver) arranged to receive analog radio signals, then select those belonging to a chosen bandwidth, then convert the selected analog signals into digital signals before demodulating them.
When the receiver (or transceiver) is designed to work in a multi-standard environment, it may also convert and process unwanted interferers which may desensitize it and hence decrease the receiving quality.
Several solutions have been proposed to suppress the unwanted interferers.
A first conventional solution consists in using an analog pre-filter before the analog-to-digital converter (ADC), and a digital filter after the ADC. The analog pre-filter, which defines the baseband part of the receiver, comprises a cascade of filters and programmable gain amplifiers (PGAs). The cascade of filters reduces interference to a chosen level to avoid an ADC overload, whereas the PGAs limit the signal under a pre-defined chosen level to reduce the dynamic range of the ADC.
Every analog component adds noise and distortion, which reduces the sensitivity of the receiver. Moreover, the offset and gain or phase error are accumulating factors and a lot of calibration and control loops are needed for correction, which increases the design time, the complexity and the risks.
A second solution consists in using a full-digital architecture, without any analog filter or PGA. The whole signal processing (filtering and scaling of word lengths) takes place in the digital domain, which offers a high flexibility. For instance one uses a sigma-delta (ΣΔ) ADC (which offers a low power consumption and anti-aliasing filter features) followed by a channel filtering, an interference filtering and a noise-shaping digital filtering.
As the interference filtering takes place after the analog-to-digital conversion, the analog signals inputted in the ADC comprise the wanted signals as well as the unwanted ones. Therefore, the bandwidth and the dynamic range of the ADC need to be very high. Moreover, the ADC needs to be extremely linear to prevent the risk of intermodulation distortion of large interferers which would disturb the reception of wanted signals belonging to a weak channel, as is the case in the UMTS standard with the UTRA/FDD band II interferers. Due to these drawbacks, the full-digital architecture requires a lot of power.
A third solution consists in using a sigma-delta (ΣΔ) ADC including an interference filter function.
Such a solution is described in the document by K. Philips et al: “A 2 mW 89 dB DR Continuous-Time ΣΔ ADC with Increased Immunity to Wide-Band Interferers”, ISSCC Dig. Tech. Papers, pp 86-87, February 2004. The filtering is realized in the ADC by adding a high-pass feedback path to a conventional ΣΔ ADC and a compensating low-pass filter in the forward path to maintain stability. The presented solution shows an input-referred dynamic range of 89 dB in 1 MHz bandwidth and a power consumption lower than 2 mW. An n-th order continuous-time feedback or feedforward topology inherently provide an anti-aliasing filtering.
An n-th order continuous-time feedback topology has an n-th order low-pass filter signal transfer function (STF) at high frequencies, whereas an n-th order continuous-time feedforward topology has a first-order low-pass filtering STF at high frequencies. Therefore the n-th order continuous-time feedback topology provides more filtering than the n-th order continuous-time feedforward topology and is more prone to be used for filtering. Unfortunately, the latter filtering becomes efficient when the interferers are at least one decade above the upper edge of the bandwidth concerned. So it is not really suited to highly digitized multi-standard and/or multi-mode receivers (or transceivers) and more precisely to the co-banding of TDMA, CDMA and W-CDMA.
The third solution is also described in the patent document WO 01/03312. Here one uses a distributed weighted feedforward topology and a distributed weighted feedback topology to feed a series of integrators respectively with the analog signals to be converted and with the digital signals outputted by a quantizer. With such a dual topology one is supposed to be capable of introducing at least one “notch” in the signal transfer function (STF) of the ADC thus allowing suppression of the unwanted interferers belonging to the frequency band corresponding to the notch.
However, the number of notches which can be introduced depends on the order (L) of the filter (i.e. the number of integrators). The number of notches is effectively limited to L/2 when the order (L) of the filter is even, and to (L−1)/2 when the order of the filter is odd. Therefore, to introduce a notch the filter order must be greater than or equal to 2, which excludes the first-order filters often used in the so-called MASH structures, such as MASH-2-1, MASH-1-2, MASH-1-1 and MASH-1-1-1.
Moreover, the implementation of notch(es) neutralizes two poles of the STF, which reduces the far filtering from 20*L dB/decade to 20*[L−(2*n)] dB/decade where n is the number of notches.
What is more, the noise transfer function (NTF) is bound to the distributed weighted feedforward topology used.
Still more, this solution is simulated with a linearized quantizer gain equal to 1. But this is not realistic because when the gain is equal to 1 the signal amplitude at an integrator output can saturate the next integrator which can strongly damage the signal-to-noise ratio (SNR) of the ADC. Moreover, in practice the quantizer is strongly not linear, so that it is important to keep a sufficiently high gain to guarantee the “high signal” stability in the ADC loop.